A prior art phase lock loop (“PLL”) circuit (also referred to as a phase-locked loop circuit) typically includes a phase detector, a filter, and a variable frequency oscillator, the latter of which typically is a voltage-controlled oscillator. The phase detector detects a phase difference between a reference signal and a feedback signal from the variable frequency oscillator. The phase detector sends a signal to the oscillator via the filter in order to adjust the frequency of the oscillator such that phases of reference signal and the feedback signal match.
Phase lock loop circuits are typically used for electronics for signal recovery, signal stability, and signal generation, such as frequency synthesis. Phase lock loop circuits generate high speed clocks with low jitter for Peripheral Component Interconnect Express (“PCIe”) devices, Quick Path Interconnect (“QPI”) devices, and other high speed input-output (“IO”) devices. Phase lock loop circuits are also used for radio frequency (“RF”) integrated circuit (“IC”) chips.
The filter in a prior art phase lock loop circuit is typically called a loop filter. The filter typically is a low-pass filter. The filter typically helps the phase lock loop circuit better handle changes, such as changes to the reference frequency, changes in the feedback signal, and changes at startup. The filter helps to determine lockup time and damping. The filter also helps to limit the amount of frequency ripple between the output of the phase detector and the input of the oscillator.
A resistor-capacitor (“RC”) loop filter has been used extensively in the prior art in phase lock loop designs. One disadvantage of a conventional RC loop filter is that in 32 nanometer (“nm”) metal gate complementary metal-oxide semiconductor (“CMOS”) logic technology, an RC loop filter typically cannot meet tight PLL bandwidth and jitter peaking specifications, such as for PCIe generations 2 and 3. One reason is the resistor variation across process, voltage, and temperature (“PVT”).
For a conventional RC loop filter, the voltage drop on the resistor (the proportional control term) typically has a fixed magnitude of Vprop=R·Icp and a varying pulse width. The pulse width is the phase difference (also called phase error) between the reference clock and the feedback clock. Given this, another disadvantage of a conventional RC loop filter is that given that the phase error does not drop to zero in the PLL locked condition due to leakage current and mismatches, there typically will be a chain of narrow pulses of voltage Vprop superimposed on the control voltage Vct1. These periodic narrow voltage pulses typically cause systematic jitter in the output clock at the reference clock period. In the frequency domain, this periodic variation in clock period is called a reference spur.
FIG. 1 shows the design of an example of a prior art switched capacitor loop filter 10. Capacitors 2 and 3 are typically reset to an inductor capacitor voltage-controlled oscillator (“LC-VCO”) control voltage that is generated by a unit gain buffer 5. Unit gain buffer 5 is an analog circuit that typically requires the prior art switched capacitor loop filter 10 to have a high open loop gain and a low input offset at the differential inputs.
A disadvantage of the prior art switched capacitor loop filter 10 is that as process scaling gets to a 32 nm node and below, it typically is very difficult to design the loop filter to have high gain and a low input offset differential amplifier without supporting circuits that increase the area of the loop filter and raise power consumption. Such supporting circuits typically include analog bias generators, circuitry for an external reference current, and circuitry for offset cancellation.
Another disadvantage of the prior art loop filter 10 is that the charge pump capacitor 1 is typically relatively large—for example, 7 picofarads (“pF”). The charge pump capacitor 1 typically determines the loop bandwidth and jitter peaking of loop filter 10.